View PMB2341_8180905.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

wireless components 10-pin single pll pmb 2341 version 1.0 specification february 2000 ds 1
edition 03.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i. gr. 21.02.00. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits im- plemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ? get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect its safety or effectiveness of that device or system. 1. 2life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? - 2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. revision history: current version: 02.2000 previous version:data sheet page (in previous version) page (in current version) subjects (major changes since last revision) 4-6 4-6 programming of multifunctional output pin (mfo) is changed, i.e. mfo (open drain) is driven to ground for mfo bit equal to 1.
productinfo product info pmb 2341 preliminary wireless components confidential specification, february 2000 package productinfo general description the pmb 2341 is a monolithic, low power, high performance phase-locked-loop (pll) frequency synthesizer. it is primarily designed to be used for very stable low noise lo signals in mobile communication systems such as gsm, pcn (gsm 1800), pcs and pdc. the wide range of divider rations also allows application in modern analog systems. features b6hfc bicmos technology 2.7 to 4.5 v operation low operating power consumption programmable power down modes high input sensitivity and high input fre- quencies up to 2.5 ghz reference frequencies up to 100 mhz. programmable dual modulus prescaler divide ratio (1:64/65 or 1:32/33). dividing ratios: a, n, r counter: 0 to 63, 3 to 4095, 3 to 4095, respectively fast phase detector with switchable polarity charge pump output with programma- ble current and without dead zone fast serial 3-wire bus interface with low threshold voltage schmitt-trigger inputs one multi-functional port very small mini-tssop-10 package ordering information type ordering code package pmb 2341 mini-tssop-10 3.0 5.0 0.2 0.5 3.0 max. high:1.2 dimens. in mm
1 table of contents 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.2 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.3 stand-by / power down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 4 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 programing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 register, data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 special programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 5 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 absolute maximum range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 operational range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 typical power-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4 typical supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.5 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.6 serial control data format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.7 rf input sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
2 product description 2.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 contents of this chapter
product description 2 - 2 pmb 2341 preliminary wireless components confidential specification, february 2000 2.1 overview the pmb 2341 is a monolithic, low power, high performance phase-locked-loop (pll) frequency synthesizer. it is primarily designed to be used for very stable low noise lo signals in mobile communication systems such as gsm, pcn (gsm 1800), pcs and pdc. the wide range of divider rations also allows application in modern analog sys- tems. 2.2 features b6hfc bicmos technology 2.7 to 4.5 v operation low operating power consumption programmable power down modes high input sensitivity and high input frequencies up to 2.5 ghz reference frequencies up to 100 mhz. programmable dual modulus prescaler divide ratio (1:64/65 or 1:32/33). dividing ratios: a, n, r counter: 0 to 63, 3 to 4095, 3 to 4095, respectively fast phase detector with switchable polarity charge pump output with programmable current and without dead zone fast serial 3-wire bus interface with low threshold voltage schmitt-trigger inputs one multi-functional port very small mini-tssop-10 package 2.3 package outline figure 2-1 mini-tssop-10 0.09 0.1 3 0.42 -0.1 +0.15 +0.08 -0.05 0.125 6 max. h a 0.1 4.9 m 0.25 a b c 3 0.1 c b a 0.08 m 0.22 0.05 0.15 max. 0.1 0.85 1.1 max. a c b 0.5 index marking
3 functional description 3.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 pin definition and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.2 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.3 stand-by / power down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 contents of this chapter
functional description 3 - 2 pmb 2341 preliminary wireless components confidential specification, february 2000 3.1 pin configuration pin_config.wmf figure 3-1 ic pin configuration 3.2 pin definition and functions pin no. symbol function 1 vdd digital cmos supply voltage. note: vdd and vcc must be equal! 2 cp pll charge pump output 3 gnd analog / bipolar ground, charge pump ground and digital cmos ground (vss) used for bipolar prescaler, charge pump and digital cmos 4 lo rf frequency input ac coupling is required. 5 vcc analog / bipolar supply and charge pump supply used for bipolar prescaler, input buffer and chargepump note: vdd and vcc must be equal! 6 mfo multi-functional output (open-drain) 7 clk 3-wire bus input: clock clock input of the serial control interface with cmos schmitt-trigger input stage 8 da 3-wire bus input: data data input of the serial control interface withcmos schmitt-trigger input stage.the serial data are read into the addressed internal shift register with the positive edge of clk 9 en 3-wire bus input: enable enable input of serial control interface with cmos schmitt-trigger input stage. when en=h the input signals clk and da are disabled. when en=l the serial control interface is enabled. the received data bits are transmitted into the addressed registers with the positive edge of en 10 ri reference frequency input input with highly sensitive preamplifier. with small input signals ac coupling must be set up, whereas dc coupling can be used for large input signals ri en da clk mfo vdd cp gnd lo vcc 1 2 3 4 5 10 9 8 7 6 pmb 2341
functional description 3 - 3 pmb 2341 preliminary wireless components confidential specification, february 2000 3.3 block diagram block_diag.wmf figure 3-2 main block diagram 1 2 3 4 5 vdd cp gnd lo vcc 10 9 8 7 6 ri en da clk mfo pll 12 bit r-counter data&shadow register phase detector 12 bit n-counter 6 bit a-counter data&shadow register modulus control 64/65 32/33 control register serial control logic ri_sby mfo enable logic buf_en pll_en sync load mod progmode mfo vcc gnd presc_sby presc cppw0,cppw1 pdpol pll_en buf_en presc_sby ri_sby nt_sby pll_stbmod nt_sby
functional description 3 - 4 pmb 2341 preliminary wireless components confidential specification, february 2000 3.4 functional blocks 3.4.1 general information the PMB2341 consists of a dual band single pll. the device is designed to work in mobile communication systems and can handle vco input frequencies up to 2.5 ghz. 3.4.2 pll the pll in the pmb 2341 consists of a high frequency bipolar configurable 32/33 or 64/ 65 dual modulus prescaler, an a- and a n-counter with dual modulus control logic, a reference- (r-) counter, and a phase detector with charge pump output with programmable output current drive capability. the counter and mode settings of the synthesizer are programmed via a serial 3-wire interface. the reference frequency is applied at the ri-input and divided by the pll ? s r-counter. its maximum value is specified to be 100 mhz. the vco ? s rf input signal is divided by the bipolar prescaler with a programmable 32/33 or 64/65 divider ratio and the following programmable a/n-counters. for a wide range of divider ratios, both n and r counter can be programmed from 3 to 4095 . the phase and frequency detectors with the charge pumps have a linear operating range without dead zone for very small phase deviations. the operating modes allow the selection of 4 different charge pump output currents, polarity setting of the phase detector, 2 standby modes and the conrol of the multi- functional output port mfo.
functional description 3 - 5 pmb 2341 preliminary wireless components confidential specification, february 2000 figure 3-3 frequency detector output waveforms frequency setting / divider ratio calculation: the frequency of an external vco controlled by the pmb 2341 is given below: with . f vco : frequency of the external vco f ri : reference frequency n: divide ratio of the n-counter a: divide ratio of the a-swallow counter p: divide ratio of the prescaler (33 in case of 32/33 prescaler selected) r: divide ratio of the r-counter m=p*n+a: total divide ratio note: for continuous frequency steps following condition is necessary further restrictions have to be fullfilled: p-channel tri-state. p-channel tr i - s t a t e . ri cp cp (ri:r) (lo:m) positive polarity n-channel frequency f v > f r f v leading frequency f v = f r lock state frequency f v < f r f v lagging f r f v lo n-channel negative polarity f vco pn ? () a + [] f ri r ------ - ? m r ---- -f ri ? == pn a + ? [] pp1 ? () ? ap < an
functional description 3 - 6 pmb 2341 preliminary wireless components confidential specification, february 2000 3.4.3 stand-by / power down conditions the pmb 2341 device has 2 different stand-by modes to reduce the power consumption. the standby modes allow separate power up and down modes for the pll itself and for the ri input amplifier circuitry. the selection of a desired power-down mode is done by setting two bits ? standby1 ? and ? standby2 ? located in the a/n-counter control word (see table 4-1: a/n counter data format). this enables a fast wake-up of the device and programming of a vco-frequency with only one bus cycle! the encoding of the defined modes can be obtained from table 4-5: standby mode selection bits.
4 applications 4.1 programing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 register, data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 special programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 contents of this chapter
applications 4 - 2 pmb 2341 preliminary wireless components confidential specification, february 2000 4.1 programing general information: programming of the ic is done via the 3 wire serial data interface consisting of a clock line, data line and an enable line. data are shifted into the device with every rising clk edge and are overtaken into internal registers with the rising edge of en according to the schematic timing diagram shown in figure 4-1. figure 4-1 schematic bus signal timing depending on the desired functional units to be programmed, several serial data formats exist. a common fact is that all multibit values are ordered in little endian notation in the bitstream meaning their msb is sent first. every bus cycle starts with the dedicated data bits followed by at least 1 register address bit and is terminated with two device address bits. in chapter 4.2 register, data format the available data formats are explained. the short control data format allows a fast pd-current change. the long control data format allows the programming of 4 different pd-output current modes for the pll, polarity setting of the pd-output signals, 2 standby modes, test mode select and the prescaler divide ratio. the a/n-counter data format contains the a/n-counter values, the multifunctional output bit and standby mode switch bits. the r-counter data format contains the r-counter values and pll programming mode switch bit. the pll is programmed in an asynchronous mode: the serial data is written directly to the data registers of the addressed counter with the enable pulse. as each counter is loading the new starting value after it is decremented to ? zero ? , the counters changes therefore their counter values asynchronously to the others. clk dat en latch data into internal register
applications 4 - 3 pmb 2341 preliminary wireless components confidential specification, february 2000 4.2 register, data format table 4-2 note msb of all serial data is shifted first! table 4-1 a/n counter data format pll bit-nr bit function lsb 0 0 caddr0 chip address 1 1 caddr1 2 1 raddr0 a/n register address 3 n0 n-counter 4 n1 5 n2 6 n3 7 n4 8 n5 9 n6 10 n7 11 n8 12 n9 13 n10 14 n11 15 standby1 pll on/off 16 standby2 ri input amp on/off 17 a0 a-counter 18 a1 19 a2 20 a3 21 a4 22 a5 23 msb mfo multifunc. output port 2 (mfo)
applications 4 - 4 pmb 2341 preliminary wireless components confidential specification, february 2000 table 4-2 r counter data format pll bit-nr bit function lsb 0 0 caddr0 chip address 1 1 caddr1 2 0 raddr0 r register address 3 1 raddr1 4 r0 r-counter 5 r1 6 r2 7 r3 8 r4 9 r5 10 r6 11 r7 12 r8 13 r9 14 r10 15 msb r11
applications 4 - 5 pmb 2341 preliminary wireless components confidential specification, february 2000 table 4-3 control data formats long control data format pll short control data format pll bit-nr value bit function value bit function lsb 0 0 caddr0 chip address 0 caddr0 chip address 1 1 caddr1 1 caddr1 2 0 raddr0 long control word address 0 raddr0 short control word address 3 0 raddr1 0 raddr1 4 1 raddr2 0 raddr2 5 cpcurr2 charge pump current setting cpcurr2 charge pump current setting 6 cpcurr1 cpcurr1 7 cpcurrtst charge pump current test mode cpcurrtst charge pump current test mode 8 presc prescaler division ratio 9 0n.a. required for correct operation 10 pdpol phase detector polarity 11 0n.a. required for correct operation 12 1n.a. 13 mode2 test mode selection 14 mode1 15 not used 16 not used 17 not used 18 not used 19 not used table 4-4 chip address bit bits caddr1 caddr0 description 1 0 this chip address has to be sent to access the PMB2341
applications 4 - 6 pmb 2341 preliminary wireless components confidential specification, february 2000 table 4-5 standy mode selection bits bits standby 1 standby 2 description remarks 1 1 allrun: pll is powered on. enabling or disabling of certain bipolar modules is done by turning on or off its bias currents. 1 0 not used: identical to allrun. 0 1 amprun: pll is powered off, only ri input preamplifier is powered on. 0 0 allopp: both pll and ri input preamplifier are powered off. table 4-6 port switching bits bit value description mfo 1 multifunctional output mfo is driven to ground ( vss) 0 multifunctional output mfo is driven to vdd table 4-7 charge pump current programming bits bits cpcurr 1 cpcurr 2 cpcurrtst cp current [ma] i remark 0 00 1.2 ma 1 00 2.0 ma 0 10 2.8 ma 1 10 4.0 ma 0 01 1.2 ma pump 1 1 01 1.2 ma pump 2 0 11 0.8 ma pump 1 1 11 0.8 ma pump 2 table 4-8 prescaler mode select bit bit value description presc 0 32/33 1 64/65 table 4-9 phase detector polarity select bit bit value description pdpol 0 negative polarity 1 positive polarity
applications 4 - 7 pmb 2341 preliminary wireless components confidential specification, february 2000 4.3 special programming sequences fast wake-up programming: when the circuit is connected to the supply voltage all registers are undefined. due to the fact that each counter is loading its new start value after it is decremented to ? zero ? , the start-up time of the counters with the programmed values is too long for some applications. if the device has previously been set to alloff- or amprun-mode (see table 5) afterwards is turned to operating mode allrun, the counters are starting immediatly with the preprogrammed start values. therefore for fast startup after standby the following data transfer sequence is recommended: table 4-10 test mode installation bits control bits mode 1 mode 2 mode 1 1 operate : normal operation of pll and ri buffer in installed mode. mfo pin has programmed level. 0 1 not used : identical to operate 1 0 testmode rcntout: charge pump is turned off. r-counter output at multifunctional mfo pin. 0 0 testmode ncntout: charge pump is turned off. n-counter output at multifunctional mfomfo pin. table 4-11 fast wake up data transfer sequence step serial data transfer sequence 1 long control word: ? operate ? 2 set a-/n-counter: amprun mode 3 set r-counter 4 set a-/n-counter, amprun mode 5 set a-/n-counter, allrun mode
applications 4 - 8 pmb 2341 preliminary wireless components confidential specification, february 2000
5 reference 5.1 absolute maximum range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 operational range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 typical power-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4 typical supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.5 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.6 serial control data format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.7 rf input sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 contents of this chapter
reference 5 - 2 pmb 2341 preliminary wireless components confidential specification, february 2000 5.1 absolute maximum range the maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, due to permanent damage to the device. 5.2 operational range within the operational range the ic operates as described in the circuit description. the ac/dc characteristic limits are not guaranteed. table 5-1 absolute maximum ratings # parameter symbol limit values units remarks min max 1 cmos supply voltage v dd_lim -0.3 5v with respect to related ground. 2 bipolar supply voltage v cc_lim -0.3 5v 3 difference between v cc and v dd levels |0.2| v v cc and v dd are intended to have the same level 4 applied voltage at pins clk, da, en, ri,cp v incmos_lim -0.3 v dd + 0.3 v 5 input voltage (lo) v i_bip_lim -0.3 v cc - 0.8v v 6 output current open-drain-stage (mfo) i o_od 1ma 7 total power dissipation p tot_lim t.b.d. mw 8 ambient temperature t a -40 85 c 9 storage temperature t stg -50 125 c 10 esd integrity v esd t.b.d. t.b.d. v table 5-2 operating ratings # parameter symbol limit values units l remarks min max 1 cmos supply voltage v dd 2.7 4.5 v v cc and v dd are intended to have the same level 2 bipolar supply voltage v cc 2.7 4.5 v 3 input vco frequency at lo ? lo 250 2500 mhz prescaler set to 32/33 mode 4 input vco frequency at lo ? lo 250 2500 mhz prescaler set to 64/65- mode 5 input frequency at ri f ri 1 100 mhz 6 output current open-drain- stage (mfo) | i o_pp | 0.2 ma 7 cp-output current of pll | i o_cp | 4ma 8 cp-output voltages v o_ cp 0.5 v cc - 0.5 v 9 ambient temperature t a -40 85 c
reference 5 - 3 pmb 2341 preliminary wireless components confidential specification, february 2000 5.3 typical power-on time time required to turn pll and/or lo-buffer-chain frominstalled standby-mode to mode allrun. time is measured from time point when the enable-signal is sent on 3-wire bus after programming the apropriate data bits. note 1: only the turn-on time from pll is measured, not the required lock-in time, which strongly depends on the loopfilter, etc. 5.4 typical supply current note 1) : room temperature, all supplies set to 3.2v, t a = 27 c, f ri = 13mhz, f lo = 1.2ghz, internal fref = 200khz, pll locked in mode allrun, charge pump output current set to 4ma. no bus programming activities. values may vary within 10%. table 5-3 previously installed standby mode (see table 5) turn-on- time units remarks amprun t.b.d s see note 1) alloff 1 s table 5-4 standby mode (see table 5) cmos- supply i dd bipolar supply i cc units test item test condition allrun 1.4 5.5 ma 1.1 see note 1) alloff 00 ma 1.2
reference 5 - 4 pmb 2341 preliminary wireless components confidential specification, february 2000 5.5 ac/dc characteristics ac/dc characteristics involve the spread of values guaranteed within the specified sup- ply voltage and ambient temperature range. typical characteristics are the median of the production. supply voltage v cc , v dd , , v cp = 2.7v...4.5v, ambient temperature t amb = -40 c to 85 c except especially mentioned other values note 1: f ri =4..30 mhz, v dd =3.6 v measured with pll in mode rcntout (see table 4-10) at pin mfo. table 5-5 ac/dc characteristics # symbol limit values units test item test conditions min typ max input signals (schmitt-trigger) da, clk, en when configured as input 1 h-input voltage v i_st_h 1.5v v dd v 2.1 v dd = 3.5v 2 h-input voltage v i_st_h 0.5 v dd v dd v 2.2 v dd = 3.5v 3 l-input voltage v i_st_l 0.5v v 2.3 v dd = 2.7v 4 input capacity c i_st 5pf *) guaranteed by design 5 dc high-input current i st_ h 0 5 a 2.4 6 dc low-input current i st_l 0 5 a 2.5 output signals mfo (open drain) 7 l-output voltage v o_od_l 0.01 0.1 v v 3.1 i o_od_l = 0.2 m 8 h-output current i o_od_h 0 5a 3.2 charge pump output current i o_cp 9 "1.2 ma" | i o_cp | -20% 1.2 +20 % ma 4.1 v cp = 3.2v, v o_cp = v cp /2 10 "2 ma" | i o_cp | -20% 2.0 +20 % ma 4.2 11 "2.8 ma" | i o_cp | -20% 2.8 +20 % ma 4.3 12 "4 ma" | i o_cp | -20% 4.0 +20 % ma 4.4 13 "4 ma" | i o_cp | -20% 4.6 +20 % ma 4.5 v cp = 4.5v 14 "leakage current" | i o_cp | 0.1 1*) na 4.6 *) guaranteed by design output tolerance i o_cp with variing voltage at pin cp 15 ? i o_cp / i o_cp -10% 5.1 v o_cp = 0.5...- v cp -0.5v crystal oscillator input signal ri 16 input voltage at ri v i_ri 100 mv rms 6.1 v dd = 2.7v, note 1) input at lo; vcc=3.6 v 17 input voltage at lo v i_lo -20 -9 +4 +4 dbm dbm 7.1 7.2 500 - 2500 mhz 250 - 500 mhz
reference 5 - 5 pmb 2341 preliminary wireless components confidential specification, february 2000 5.6 serial control data format timing figure 5-1 serial control data format timing table 5-6 symbol limit values units min max parameter clock frequency ? clk 15 mhz h-pulsewidth (clk) t whcl 30 ns data setup t ds 20 ns setup time clock-enable t cle 20 ns setup time enable-clock t ecl 20 ns h-pulsewidth (enable) t when 60 ns rise, fall time t r , t r 10 s propagation delay time en-port t dep 1 s v il v ih v ih v il v ih v il v ih v il t whcl t when t ecl t cle t ds t dep clk da en port t f t r
reference 5 - 6 pmb 2341 preliminary wireless components confidential specification, february 2000 5.7 rf input sensitivity figure 5-2 rf input sensitivity measured prescler rf sensitivity (vcc=2.7v, 64/65 divider) -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 50 300 550 800 1050 1300 1550 1800 2050 2300 2550 2800 3050 3300 input frequency [mhz] input power [dbm] baseline top line

▲Up To Search▲

Price & Availability of PMB2341

	To Download PMB2341 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .